The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2001
Filed:
Jun. 27, 1997
Hideyuki Emura, Tokyo, JP;
Koichi Sato, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
An apparatus for optimization of circuit design such as integrated circuits and printed circuits and an optimization process of the initial layout circuit, from results of the initial layout of the circuits, circuit connection informations after layout, cell positions, and interconnection routing, capacitance and resistance of interconnections are fetched. Optimization is made by local modification to the circuit such as cell placement and buffer insertion in consideration of keeping cell placements and interconnection routing so as to reduce delay, power consumption and circuit scale. Layout information to be changed by the local modification to the circuit is accurately recalculated on the basis of the original layout information. Renewed circuit connection information and newly calculated layout information are transmitted as restriction requirements to the layout section for conducting the relayout.