Eprom circuit with error correction

Abstract

To correct an unintentionally erasing error in an EPROM circuit, in accordance with the same one-bit data, each of first and second EPROM cells is either unprogrammed to output a first logic value representing an unprogrammed condition when reading or programmed to output a second logic value representing a programmed condition when reading. A logic operation gate outputs the first logic value when both the first and second EPROM cells output the first logic value and outputting the second logic value when at least one of the first and second EPROM cells output the second logic value. To correct unintentionally writing error in an N-bit EPROM circuit, a first parity is stored and a second parity is detected from N logic operation gates. If the first parity disagrees with the second parity, a correction signal is generated. In the presence of the correction signal, when it is detected at each of N-bit that an output of the first EPROM cell disagrees with that of the second one, an inverted output of the logic operation gate at the bit instead the output of the logic operation gate.