The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2001
Filed:
Aug. 17, 1999
Applicant:
Inventors:
M. Dwayne Ward, McKinney, TX (US);
Vikas Agrawal, Dallas, TX (US);
George B. Jamison, Dallas, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 8/00 ;
U.S. Cl.
CPC ...
G11C 8/00 ;
Abstract
A memory timing architecture which very accurately tracks the read and write timing of a memory over a wide range of array sizes, with separate read and write timing circuits. The read reset circuitry uses a plurality of dummy cells to gauge the time necessary to complete the read operation, while the write reset uses a single dummy cell to gauge the time necessary to complete the write operation. These circuits provide for a more accurately-timed feedback signal, which allows for increased speed while at the same time reducing power consumption and heat buildup.