The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2001
Filed:
Nov. 09, 1999
Applicant:
Inventors:
Assignee:
NEC Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 1/500 ;
U.S. Cl.
CPC ...
G11C 1/500 ;
Abstract
A semiconductor memory (,) is disclosed that includes a memory cell array (,) coupled to a register array section (,) that can function as a cache. Access times for misses to the register array section (,) during a continuous read operation can be reduced. A memory cell array (,) is coupled to the register array section (,) by a first transfer bus (TBT,-,to TBN,-,). First transfer bus (TBT,-,to TBN,-,) is connected to a local read/write bus (LRWBT and LRWBN) by transistors (,-,to,-,) and to register arrays (,-,to,-(,)) by first switches (,-,to,-(,)). In a continuous read operation, during a register array section miss, transistors (,-,to,-,) are turned on and the first switches (,-,to,-(,)) are turned on.