The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2001
Filed:
Feb. 18, 2000
John G. Tracy, Raleigh, NC (US);
Edward Akbari, Etobicoke, CA;
Miguel E. Chavez, Raleigh, NC (US);
Frederick Tassitino, Jr., Wake Forest, NC (US);
Powerware Corporation, Raleigh, NC (US);
Abstract
Uninterruptible power supplies (UPSs), power conversion apparatus and power conversion methods are provided which may improve phase regulation of polyphase AC voltages in the presence of load imbalances. According to one embodiment, a UPS includes a DC voltage generating circuit that produces a DC voltage. A space vector domain controlled inverter couples the DC voltage generating circuit to an AC load, and produces a polyphase AC output voltage at the load by sensing a plurality of voltages at the load, transforming the plurality of sensed voltages according to a space vector (d-q) transformation to produce an output space vector, generating an error space vector from the output space vector and a reference space vector, and selectively coupling the DC voltage generating circuit to the load responsive to the error space vector. In this manner, a voltage control loop is closed in the d-q domain, which may improve per-phase regulation of the polyphase AC output. Preferably, compensation is applied to the error space vector to produce a control space vector that compensates for poles or other transfer characteristics of the forward path of the voltage control loop. In another embodiment, the reference space vector is generated by an outer voltage amplitude loop that compares a sum of the plurality of output voltages at the load to a reference voltage amplitude, generating an error amplitude voltage which is compensated and then transformed according to a space vector transformation to produce the reference space vector that serves as the set point for the inner space vector domain control loop.