Differential sense amplifier with reduced hold time

Abstract

A sense amplifier includes cross-coupled n-transistors that provide, from a predetermined time during one sample period to the start of the next precharge period, a path from a discharging internal node to the low supply voltage VSS. The n-transistors provide a discharge path from the time the internal node falls sufficiently below a precharge voltage to cause the transistors to operate differentially, until the time the node is again precharged, regardless of changes in the state of the input signals. The gate voltages of the cross-coupled transistors are controlled by the internal nodes, and the transistors participate in a positive feedback loop that drives the non-discharging internal node to a high supply voltage VDD through a cross-coupled p-transistor that is controlled by the discharging node. For a sense amplifier that precharges the pre-output nodes low, cross-coupled p-transistors similarly provide a path to VDD to charge the pre-output nodes from a point in one sample period to the start of the next precharge period, regardless of changes in the state of the input signals.