The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 06, 2001
Filed:
Jan. 27, 1999
Yasunao Katayama, Hachiohji, JP;
Shigenori Shimizu, Machida, JP;
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention provides a memory system that optimizes, during a sleep mode, a refresh period for a memory device, such as DRAM, which stores meaningful data and for which a refresh operation is required to prevent the loss of data. More particularly, the present invention is directed to an apparatus for controlling, in a sleep mode, a refresh period for a memory device,that requires a refresh operation, comprises: an encoding circuit,for encoding data to obtain code that can be used to correct errors equal to or more than dual errors; a decoding circuit,for correcting errors and for decoding the corrected code; and a refresh period controller,for, following a transition to the sleep mode, changing a refresh period by using data, which is stored in the memory device,and encoded by the encoding circuit,, until the refresh period becomes longest in a condition where there is no error that can not be corrected by the decoding circuit,and the number of correctable errors does not exceed a predetermined count, and where a refresh execution circuit,for performing the refresh operation for the memory device can deal with the changed refresh period, and for, following the first end of the change of the refresh period, setting the refresh execution circuit,so that the refresh of the memory device,is performed at the refresh period at the first end of the change of the refresh period.