System and method for aligning an initial cache line of data read from an input/output device by a central processing unit

Abstract

A computer is provided having a bus interface unit coupled between a CPU bus, a PCI bus and/or a graphics bus. The bus interface unit includes controllers linked to the respective busses and further includes a plurality of queues placed within address and data paths linking the various controllers. A processor controller coupled between a processor local bus determines if an address forwarded from the processor is the first address within a sequence of addresses used to select a set of quad words constituting a cache line. If the address (i.e., target address) is not the first address (initial address) in that sequence, then the target address is modified so that it becomes the initial address in that sequence. Quad words are received in sequential order and placed into the queue. When the quad words are sent to the CPU, they are in toggle order. This ensures the processor controller, and eventually the processor, will read quad words in toggle mode address order, even though the quad words are dispatched from the peripheral device in address-increasing (non-toggle mode) order.