The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 06, 2001

Filed:

Dec. 24, 1997
Applicant:
Inventors:

James Douglas Dworkin, Chandler, AZ (US);

Michael John Torla, Chandler, AZ (US);

P. Michael Glaser, Tempe, AZ (US);

Ashok Vadekar, Mississauga, CA;

Robert John Lambert, Hespeler, CA;

Scott Alexander Vanstone, Waterloo, CA;

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/72 ; H04L 9/28 ;
U.S. Cl.
CPC ...
G06F 7/72 ; H04L 9/28 ;
Abstract

An elliptic curve (EC) processor circuit (,) comprising a finite field arithmetic logic unit (,), operation registers (,) an EC control unit (,) and a register file (,). A storage element (,) is coupled to the finite field arithmetic logic unit (,). The EC control unit (,) controls the various components of the EC processor circuit (,) to decompress a compressed one-bit representation of a Y coordinate of an elliptic curve point (X, Y). The EC control unit (,) controls the use of the operation register (,), the storage element (,) and the finite field arithmetic logic unit (,) to recursively compute the decompressed version of the compressed Y coordinate based upon the X coordinate and the compressed one-bit representation of the Y coordinate. The circuit and method employ minimal additional hardware and processing in an EC processor circuit (,).


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