The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 06, 2001

Filed:

Dec. 09, 1999
Applicant:
Inventors:

Hiroyuki Sugamoto, Kasugai, JP;

Takaaki Furuyama, Kasugai, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 ;
U.S. Cl.
CPC ...
G11C 7/00 ;
Abstract

A semiconductor memory, such as an SDRAM, includes a data bus pair, a first reset circuit, a second reset circuit and a control circuit. The first reset circuit is connected between the buses of the data bus pair and resets the buses at a first potential. The second reset circuit is also connected between the data buses and resets the buses at a second potential. The control circuit is connected to the first and second reset circuits and activates the first reset circuit and deactivates the second reset circuit prior to a write operation. The control circuit further deactivates the first reset circuit and activates the second reset circuit prior to a read operation.


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