Semiconductor memory device

Abstract

The semiconductor memory device formed on a semiconductor substrate includes: a memory cell array having a plurality of memory cells formed at intersections between a plurality of word lines and a plurality of bit line pairs; a plurality of sense amplifiers each formed to correspond to each of the plurality of bit line pairs for amplifying a potential difference read on the bit line pair; and a low-level potential generation section for generating a low-level potential out of high-level and low-level potentials to be applied to the memory cells, the bit line pairs, and the sense amplifiers. The low-level potential generation section has: a ground potential generation part having a ground potential generation semiconductor element for generating as the low-level potential a first potential substantially equal to a ground potential; a threshold potential generation part having a threshold potential generation semiconductor element for generating as the low-level potential a second potential substantially equal to a threshold potential, and operating when a potential exceeding the threshold potential is applied; and a ground potential control part for controlling operation of the ground potential generation semiconductor element.