Phase locked loop having direct digital synthesizer dividers and improved phase detector

Abstract

A digital phase locked loop (PLL) frequency synthesizer having the conventional voltage controlled oscillator (VCO) divider in the feedback loop to the phase detector replaced with a direct digital synthesizer (DDS) divider. In accordance with the principles of the present invention, the reference divider in the input path may also be replaced with a DDS divider. Moreover, a new architecture for the phase detector and current digital-to-analog converter (DAC) which operate on the instantaneous phase of each DDS is provided. Thus, in accordance with the principles of the present invention, the update rate of the digital PLL frequency synthesizer is not based on the frequency signal output from the reference divider in the input path (as in conventional digital PLL frequency synthesizer architectures). Rather, the update rate is based on fixed clock signals output from the clock generator, which utilizes the master clock and the output frequency, in accordance with the principles of the present invention. The digital PLL frequency synthesizer is capable of a very high update rate, very fast settling time, and very fine frequency control.