The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 06, 2001

Filed:

Oct. 26, 1999
Applicant:
Inventor:

Shufan Chan, Anaheim Hills, CA (US);

Assignee:

Integrated Power Technologies, Inc., Anaheim Hills, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/44 ;
U.S. Cl.
CPC ...
G05F 1/44 ;
Abstract

A dead time regulating apparatus is used in a switch mode power system. The apparatus, comprises a power MOSFET circuit with PMOS and NMOS devices. Driving means is connected for driving and for turning-on a delay in the MOSFETs. A time delay detecting means is connected for detecting dead time during MOSFET turn on and a pulse width comparing means is connected for receiving dead time signals and synchronous pulses for generating control signals. The control signals are directed to the driver means respectively for adjusting turn-on delays. The method of the invention provides precise dead time control in the MOSFET devices. The circuit drives the two MOSFET devices such that there is precise control of the dead time during on-off switching.


Find Patent Forward Citations

Chan, Shufan. (2001). Power mosfet switching dead time control method and apparatus (U.S. Patent No. 6198263). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6198263

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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