The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 2001

Filed:

Oct. 09, 1998
Applicant:
Inventors:

Andrew Leaver, Milpitas, CA (US);

Francis B. Heile, Santa Clara, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract

A method and mechanism for mapping heterogeneous logic elements in a portion of electronic design compilation for a programmable integrated circuit is disclosed. Specifically, the invention provides a method to perform the technology mapping of heterogeneous logic elements in a programmable logic device such as selectively choosing the best combination of product term logic elements and look up table logic elements.


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