Semiconductor device having semiconductor memory circuit to be tested, method of testing semiconductor memory circuit and read circuit for semiconductor memory circuit

Abstract

Disclosed herein is a semiconductor device having a semiconductor memory circuit whose operation is tested in combination with an external test means to specify defective portions produced in a memory section of the semiconductor memory circuit and shorten the time necessary for its test. The present semiconductor device comprises a test pattern generator for generating a test pattern indicative of the type of test and an expected value estimated to be obtained by the test pattern in response to a command issued from the test means, the semiconductor memory circuit, which has a plurality of memory cells disposed in the form of a matrix with rows and columns and respectively store data therein and is activated based on the test pattern so as to output data in the respective memory cells every columns, a decision unit for comparing each output data with the expected value and outputting the result of comparison therefrom and a translation unit for converting the result of comparison into address data and outputting it to the external test means.