The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 2001

Filed:

Mar. 26, 1998
Applicant:
Inventor:

Kazuyuki Kawashima, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/107 ;
U.S. Cl.
CPC ...
G06F 1/107 ;
Abstract

The present invention provides a trouble releasing system wherein, in operation of an ATM logic IP subnetwork, interruption of communication by a stop of an address solution server is prevented. When a currently used NHS,which performs address solution in a logic IP subnetwork stops a server operation because of a trouble thereof, a standby NHS control unit,in a standby NHS,issues an instruction for change-over to a server operation, and consequently, the standby NHS,operates as a server for address solution. Further, an NHC control unit,in an NHC,retrieves an address of the standby NHS,registered in a server address database,and causes the standby NHS,to switchably perform communication of an address solution request.


Find Patent Forward Citations

Kawashima, Kazuyuki. (2001). Trouble releasing system and method for atm logic ip subnetwork (U.S. Patent No. 6195329). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6195329

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…