Semiconductor memory with floating gate type fet

Abstract

A source region and a drain region are formed in a surface layer of a semiconductor substrate on both sides of a channel region defined in the surface layer. A tunneling insulating film is formed on the channel region, the tunneling insulating film having a thickness which allows carriers to tunnel therethrough. A floating gate electrode is formed on the tunneling insulating film, the floating gate electrode being disposed so as to overlap neither the source region nor the drain region as viewed along a substrate normal direction. A gate insulating film is formed over the channel region, covering the floating gate electrode. A control gate electrode is formed on the gate insulating film, the control gate electrode being disposed so as to become in contact with, or partially overlap, the source and drain regions as viewed along the substrate normal direction. Materials of the floating gate electrode and channel region are selected so that a Fermi level of the floating gate electrode is positioned in an energy band gap of the channel region when an external voltage is not applied between the channel region and the control gate electrode.