The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 27, 2001
Filed:
May. 05, 1999
Applicant:
Inventor:
Hiroshi Shigehara, Machida, JP;
Assignee:
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/01 ;
U.S. Cl.
CPC ...
H03K 3/01 ;
Abstract
When a power supply terminal (,) is grounded, a circuit (,) is in the OFF state, and a high potential is transferred from a circuit (,) to a bus line (BL), the high potential is transferred to a node (,) via the source of a transistor (P,), back gate (Nw), and transistor (P,). A NAND circuit (NA,) always outputs a control signal (VGP) of a level equal to the node (,) to the gate of the transistor (P,) to turn non-conductive the transistor (P,). Hence, a current path from a terminal (B) to a terminal (A) or from the terminal (B) to the back gate (Nw) is cut off to prevent wasteful current consumption.