The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 27, 2001
Filed:
Apr. 13, 1999
Seyed Ramezan Zarabadi, Kokomo, IN (US);
Mark Russell Keyse, Sharpsville, IN (US);
Pedro Enrique Castillo-Borelly, Kokomo, IN (US);
William Joseph Hulka, Kokomo, IN (US);
Delphi Technologies, Inc., Troy, MI (US);
Abstract
A DC offset compensation circuit (,) for compensating for a DC offset voltage of a signal amplifier (,) includes a first sample and hold circuit (,) having an input receiving an amplifier output signal (VOUT,) and an output supplying the sampled and held output signal (VOUT,) to a non-inverting input of a comparator,A first digital-to-analog (D/A) circuit (,) is responsive to a number of digital input signals to produce an analog DC target signal at an output (V,) thereof. The analog DC target signal is provided to an input of a second sample and hold circuit (,) having an output supplying the sampled and held analog DC target signal to an inverting input of the comparator,The output of the comparator,is provided to an offset cancellation control circuit (,) including a state machine (,) and a counter circuit (,) operable to modify a count value (OFFDAC) thereof depending upon statuses of a number of input control signals (CLK,CLK,STRT, STP) and the comparator output signal (CO). A second D/A circuit has a number of digital inputs receiving the count value (OFFDAC) and producing at an output (VDCO) thereof an analog DC compensation signal corresponding thereto. The analog DC compensation signal is provided to a input (VDCO) of the signal amplifier (,) to thereby force the DC component of the amplifier output signal (VOUT,) near the analog DC target signal, thereby minimizing an aggregate DC offset voltage attributable to the signal amplifier (,).