The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 27, 2001
Filed:
May. 19, 1999
Matthew P. Crowley, San Jose, CA (US);
Amos Ben-Meir, Cupertino, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
In a data processing system, a circuit for providing an even bus clock signal, EVENB,, when the leading edges of the bus clock signal B,and a processor clock signal P,are coincident includes a phase-locked loop unit and a coincidence unit. The phase-locked loop unit provides P,signals that have a frequency Nx the frequency of the B,signals, where N can have an integer or a half integer value. The phase-locked loop unit includes a divide-by-M unit, where M=2N, that receives the P,signal at an input terminal and applies an output signal, P,/M, to the phase detector unit of the phase-locked loop unit. The operation of the phase-locked loop results in the B,signal and the P,/M signal having an established phase relationship. The P,signal and the P,/M signal are applied to the coincidence unit, the simultaneous application of the two signals resulting in the coincidence unit providing the EVENB,signals. When N is an integer, the P,signal and the B,signal have coincident rising edges that do not coincide with a leading edge of a P,/M signal. In this situation, a delayed signal, triggered by a previous P,/M signal, is generated that is applied to the coincidence unit in place of the missing P,/M signal to provide the EVENB,signal.