The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 2001

Filed:

Aug. 13, 1997
Applicant:
Inventors:

Kenji Ohsawa, Kanagawa, JP;

Kazuhiro Sato, Kanagawa, JP;

Makoto Ito, Kanagawa, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/3495 ;
U.S. Cl.
CPC ...
H01L 2/3495 ;
Abstract

In a semiconductor chip, electrode pads are formed in a peripheral portion of the chip front surface and the inside of the pad forming region is made an effective device region. An insulating, thick-film protective layer is laminated on the effective device region of the semiconductor chip. Leads are constituted of outer leads that are protected by an insulating film and inner leads that are integral with and extend from the outer leads. External connection terminals are formed on the outer leads, and the tips of the inner leads are connected to the electrode pads of the semiconductor chip. A reinforcement plate is provided so as to surround the semiconductor chip. A peripheral space of the semiconductor chip is charged with a sealing resin. According to a second aspect of the invention, a semiconductor chip has electrode pads on the chip front surface and disposed inside a conductive outer ring. A film circuit is disposed on the chip front surface side. External connection terminals are formed on the film circuit so as to project therefrom. First leads electrically connect part of the electrode pads to part of the external connection terminals. A second lead electrically connects a grounding or power supply electrode pad to the outer ring, and a third lead electrically connects a grounding or power supply external connection terminal to the outer ring. A conductive stage is bonded to the chip back surface and the outer ring through respective conductive bonding layers.


Find Patent Forward Citations

Loading…