The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 27, 2001
Filed:
May. 01, 1997
Teruhiko Amano, Tokyo, JP;
Masaki Tsukude, Tokyo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
A semiconductor circuit device having a triple-well structure wherein a predetermined potential level is supplied to a top well without a contact region formed in the top well is disclosed. In an N-type ion implantation step for forming an N-type well region (,) in a P-type semiconductor substrate (,), a mask of a predetermined configuration is used so that ions are not implanted into a region of a portion which is to serve as a bottom portion (,B) of the well region (,). Then, the N-type well region (,) is formed which is shaped such that a portion (,) having P-type properties remains partially in the bottom portion (,B). The P-type portion (,) establishes electrical connection between a P-type well region (,) and the semiconductor substrate (,) to permit the potential applied to a contact region (,) to be supplied to the well region (,) therethrough. The portion (,) may include a plurality of portions (,) which allow uniform potential supply. This structure may be applied to basic cells of a memory cell array block.