The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 27, 2001
Filed:
Aug. 19, 1998
Miguel Angel Jimarez, Newark Valley, NY (US);
Reinaldo Anthony Neira, Endicott, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Receptor pad structures for chip carriers, and in particular, non-floating BLM C-4 receptor pads for organic chip carriers preferably utilizing eutectic solder. On the receptor pads of chip carriers, particularly in providing equal distributions of the solder so that all pad areas are equalized irrespective as the type and size of receptor pad configuration, there is a utilization of a solder mask constituted of an insulating material, and which incorporates specifically sized and shaped solder openings or windows wherein, in a particular instance, the C4 receptor pad is essentially at the intersection of a copper trace and the solder mask window. Pursuant to a particular aspect, the solder mask opening is of a polygonal configuration, whereas in other instances, as described hereinbelow, the C4 receptor pad design may be essentially of a socalled “band aid” or circular configuration in which a circular pad is located below and within a round solder mask opening or window. The circular pad extends within and beyond the solder mask window or opening through the intermediary of the copper trace, thereby enabling the formation of equal solder areas on all pads and eliminating the previously encountered BLM floating problem leading to potentially unreliable connections and resulting chip failures.