Hardware architectures for image dilation and erosion operations

Abstract

A hardware architecture for mathematical morphology operations such as dilation and erosion of an image signal is provided. A hardware architecture for an image dilation operation includes: a plurality of adders corresponding to the size of the structuring element for adding the image signal and a structuring element symmetrical to the image signal with respect to the origin to output the result; a plurality of stores for temporarily storing the signals output from the plural adders; a comparator for comparing data stored in the plural stores with feedback data to output the maximum data; and an outputting device for outputting the output signal of the comparator as a dilation operation value if the dilation operation with respect to all structuring elements for one image signal is completed and feeding back the output signal of the comparator as input data of the comparator if not. Therefore, the elementary operations such as dilation and erosion with respect to a gray-level image signal can be attained by a simple arithmetic operation, that is, by finding the maximum/minimum value using an adder. Also, since the hardware architecture for the dilation and erosion operations adopts a feedback structure, the volume of the hardware linearly increases even though the size of the structuring element increases in geometrical progression.