Semiconductor integrated circuit

Abstract

A clock pulse generator generates a plurality of clock pulses which has different phases during one cycle of a reference clock signal supplied from the exterior. A timing setting circuit sets a latency, which is a number of clock cycles from a start of a read operation to an output of read data, at a number which is divisible by one n-th (n=2, 3, 4 . . . ) of a cycle of the reference clock signal and outputs latency information according to the set latency. An output controlling pulse switching circuit respectively outputs each of the clock pulses as a predetermined output controlling pulse in accordance with the latency information. In other words, a plurality of the output controlling pulses are switched according to the latency information. In synchronization with each of the output controlling pulses, a data outputting circuit sequentially and respectively converts parallel data, read from a plurality of memory cells stored with data, into serial data and respectively outputs the converted serial data during the predetermined period according to the latency. No matter what timing of the reference clock signal the latency might be set at, therefore, the serial data can be reliably outputted without switching the parallel data. The data are outputted at high speed because the parallel data need not be switched.