The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 20, 2001
Filed:
Sep. 03, 1998
Takeshi Shibuya, Ibaraki-ken, JP;
Tadashi Okada, Hadano, JP;
Masayuki Kanda, Hadano, JP;
Eiji Yoshino, Hitachi, JP;
Atsushi Onose, Hitachi, JP;
Tatsuki Inuzuka, Hitachi, JP;
Toshiaki Nakamura, Hitachinaka, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
In a halftoning unit of a laser printer and the like, a high speed, high density and high gradations halftoning is realized by multi-value implementation by clustered dot concentrated dither halftoning (known as a sub-matrix method) and PWM distributing gradation among the plurality of halftone dots with a small memory and circuit. For this purpose, the value of the difference between an input gradation value n,and a threshold value n,, &Dgr;n=n,−n,, is shortened within a range of 0 to &Dgr;h and the lower s bit of &Dgr;h is removed by a round-down or round-up process. Meanwhile, a threshold array is generated from an extended threshold pattern obtained by combining threshold patterns of 2,whose threshold interval is &Dgr;h, i.e. &Dgr;Ah×K, &Dgr;h×K+1, . . . , &Dgr;×K+2,. Thereby, a halftone dot dither process in which the PWM gradation increases distributively among the 2,dots may be realized with a small scale memory and circuit.