The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 20, 2001
Filed:
Feb. 18, 2000
Günter Igel, Teningen, DE;
Hans-Jürgen Gahle, Emmendingen, DE;
Mirko Lehmann, Freiburg, DE;
Micronas GmbH, Freiburg, DE;
Abstract
A process is provided for manufacturing a layer arrangement (,) having a bump for a flip chip or similar connection. The layer arrangement has a plurality of layers (,) made of solid material and stacked into a layer stack (,). A recess (,) that extends over several layers (,) is made in the layer stack (,) transverse to the coating planes of the layers (,). A bump material (,) is placed in the recess (,). A profiling is created on the lateral boundary wall of the recess (,) by removal of layer material of different layers (,) of the layer stack (,). The profiling, starting from the surface (,) of the layer stack (,) and progressing in layers to the inside of the recess (,), has at least two indentations (,) and at least one projection (,) located between them. After the production of the profiling, a bump material (,) is brought into the recess (,) in such a way that it grasps behind the indentations (,).
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile