The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 20, 2001
Filed:
Dec. 18, 1998
Subhas Bothra, San Jose, CA (US);
Stephen L. Skala, Fremont, CA (US);
Dipu Pramanik, Saratoga, CA (US);
Philips Electronics North America Corp., New York, NY (US);
Abstract
Disclosed is a semiconductor integrated circuit device having a plurality of metallization levels of patterned metallization lines that are resistant to electromigration voiding, and methods for making the electromigration void resistant metallization lines. The semiconductor integrated circuit device includes a metallization line having a first end and a second end. Oxide feature regions are defined in the metallization line, and the oxide feature regions are arranged along the metallization line between the first end and the second end. Each one of the oxide feature regions are configured to be separated from a previous oxide feature region by about a Blech length or less, and each of the oxide feature regions are configured to define a region of increased metallization atom concentration and a corresponding increased back-flow force. The oxide feature regions therefore define a composite metallization interconnect line, which is well configured to retard electromigration voiding.