System for initiating exception routine in response to memory access exception by storing exception information and exception bit within architectured register

Abstract

A circuit and method is provided for initiating an exception routine using exception information stored within architectured registers. Exception information is generated in response to a memory access exception caused by a speculative load instruction for loading a first register data from memory. The exception information, once generated, is stored within a first register. Thereafter, an instruction for operating on data stored in a second register is received and decoded. In response, the second register is checked to determine whether the second register contained exception information. If the second register contains exception information, then an exception routine is initiated. If, however, a second register does not contain exception information, then the instruction is executed and data within the second register is used in the execution.