Superscalar instruction decoder including an instruction queue

Abstract

A superscalar complex instruction set computer (“CISC”) processor having a reduced instruction set computer (“RISC”) superscalar core includes an instruction cache which identifies and marks raw x86 instruction start and end points and encodes “pre-decode” information, a byte queue which is a queue of aligned instruction and pre-decode information of the “predicted executed” state, and an instruction decoder which generates type, opcode, and operand pointer values for RISC-like operations (ROPs) based on the aligned pre-decoded x86 instructions in the byte queue and determines the number of possible x86 instruction dispatch for shifting the byte que. The instruction decoder includes in each dispatch position a logic conversion path, a memory conversion path, and a common conversion path for converting CISC instructions to ROPs. An ROP multiplexer directs x86 instructions from the byte queue to the conversion paths, a select circuit assembles ROP information from the appropriate conversion paths, and a shared circuit processes ROP information from the select circuit for shared resources. ROP type and opcode information is dispatched from the instruction decoder to the RISC core. Pointers to the A and B source operands are furnished by the instruction decoder to a register file and to a reorder buffer in the RISC core, which in turn furnish the appropriate “predicted executed” versions of the A and B operands to various functional units in the RISC core in coordination with the ROP type and opcode information.