Shared synchronous memory with a switching circuit controlled by an arbiter and method for glitch free switching of a clock signal

Abstract

A multiple agent system allowing each of a plurality of agents, i.e., processors, to present a different address, data, control and/or clock signals to a common shared synchronous memory. The signals from each of the agents is arbitrated in response to a memory access request to determine a winning agent. The address, data, control and clock signals to the shared synchronous memory are controlled so as to prevent undesirable high frequency waveforms and/or glitches from being presented to the shared synchronous memory during an arbitration period including a transition period between the previous owner's clock signal and the winning agent's clock signal. For instance, in the case of the clock signal, a clock switching control circuit disables the clock signal to the shared synchronous memory during the arbitration period for a period of time of at least about one phase of an arbiter clock signal before the transition period and one phase of the arbiter clock signal after the transition period. In the case of the address, data and control signals, an enable disactivation signal disables the output of the address, data and control signals to the shared synchronous memory during a transition period including the arbitration period.