The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 13, 2001
Filed:
Mar. 23, 1998
Applicant:
Inventors:
Jane Grace Kehoe Cullum, Yorktown Heights, NY (US);
Albert Emil Ruehli, Chappaqua, NY (US);
Assignee:
International Business Machines Corporation, Armonk, NY (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06G 7/19 ; G06F 1/750 ;
U.S. Cl.
CPC ...
G06G 7/19 ; G06F 1/750 ;
Abstract
A method comprising a computational procedure for obtaining reduced-order models of partial element equivalent circuit (PEEC) models of very large scale integrated (VLSI) interconnects. The methodology is not limited to PEEC applications, and can be used for generating reduced-order models of other systems which can be modeled with linear, time-invariant systems of ordinary differential equations with time delays.
Cullum, Jane Grace Kehoe. (2001). Method for constructing reduced-order models of systems (U.S. Patent No. 6188974). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6188974
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile