The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 13, 2001
Filed:
Sep. 16, 1999
Kenichi Sakakibara, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
According to one embodiment, a semiconductor memory (,) can include a firststage control circuit (,) that generates a first stage control signal &phgr;0, a data input/output (DQ) control circuit (,) that generates a DQ control signal &phgr;1 based on the first stage control signal &phgr;0 and a row address enable signal RASE, and a data mask (DQM) control circuit (,) that generates a DQM control signal &phgr;2 based on the first stage control signal &phgr;0, row address enable signal RASE, and a column address strobe (CAS) latency equal to one value (CLT,). A DQ first-stage circuit (,) is coupled to the DQ control circuit (,) and a DQM first-stage circuit (,) is coupled to the DQM control circuit (,). The DQ and DQM first-stage circuits (,and,) can be deactivated when the RASE signal, CASE signals are inactive and the CAS latency is greater than one.