Programmable delay generator and application circuits having said delay generator

Abstract

A programmable delay generator comprises a first ramp wave generator and a second ramp wave generator, each having the same structure as each other, each of them operating with external common clock pulses, and each of them providing potential gradient and final potential incorporated with an external set data; a comparator for comparing an output (V,) of the first ramp wave generator and an output (V,) of the second ramp wave generator so that an output pulse is provided when the outputs of two ramp wave generators coincide with each other; said first ramp wave generator providing a first ramp voltage (V,) upon receipt of a first set data (S) at a predetermined time (t,); said second ramp wave generator providing a threshold voltage (V,) upon receipt of a second set data (K) at a time which preceds at least one clock time (T) than said predetermined time (t,); said comparator providing an output pulse delayed by delay time (t,) which is proportional to ratio (K/S) of said second set data (K) and said first set data (S) from said predetermined time. An application circuit using said programmable delay generator, including a frequency synthesizer, a frequency multiplier, a duty ratio converter, and a PLL frequency synthesizer is also provided.