The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 13, 2001
Filed:
Jan. 07, 1999
Wagdi W. Abadeer, Jericho, VT (US);
Jonathan M. McKenna, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of determining time-to-breakdown of a gate dielectric in an NFET or a PFET transistor. For an NFET transistor, the method includes providing an N+ injector ring in the p-substrate and forward biasing the N+ injector ring with respect to the p-substrate. A first positive reference voltage level is applied to the source and the drain regions. A second positive reference voltage level is applied to the gate dielectric. The first and second positive reference voltage levels are maintained on the transistor until breakdown of the gate dielectric occurs. Another embodiment of the method may be used in a PFET transistor.