The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2001

Filed:

Jun. 17, 1998
Applicant:
Inventors:

Ende Shan, San Ramon, CA (US);

Gorley Lau, Fremont, CA (US);

Sam G. Geha, Sunnyvale, CA (US);

Assignee:

Cypress Semiconductor Corp., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1477 ;
U.S. Cl.
CPC ...
H01L 2/1477 ;
Abstract

A method of forming metallic layers on a substrate includes the steps of forming a first layer including a first metal on the substrate; cooling the first layer for a period of time sufficient to suppress formation of an intermetallic phase; and forming a second layer including a second metal distinct from the first metal on the first layer. The cooling step decreases the roughness of the resultant stacked structure by suppressing the formation of an intermetallic phase layer between the two metallic layers and by suppressing “bumps” or other surface irregularities that may form at relatively reactive grain boundaries in the first layer.


Find Patent Forward Citations

Shan, Ende. (2001). Method of forming metal layer(s) and/or antireflective coating layer(s) on an integrated circuit (U.S. Patent No. 6187667). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6187667

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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