The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 06, 2001

Filed:

Nov. 07, 1997
Applicant:
Inventor:

Norimitsu Sako, Okayama, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract

A method of designing a logic circuit including pass transistors is disclosed. A logic group having a complementary variable in a given logical expression to be realized into the logic circuit is mapped using a multiplexer composed of a combination of the pass transistors. The number of transistors used in the logic circuit and the number of stages can be reduced by taking advantage of the multiplexer. When a logic circuit including both pass transistors and a multiple-input logic gate is designed, a logic group having a common variable in the given logical expression is mapped using the multiple-input logic gate. The number of transistors used in the logic circuit and the number of stages can be further reduced by taking advantage of the multiple-input logic gate. In order to ease the above mapping procedure, a complementary variable is identified and the given logical expression is optimized by grouping product terms of the logical expression by the complementary variable. Furthermore, a common variable is identified, and the logical expression is further optimized by grouping product terms of the logical expression by the common variable.


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