Device for indicating the fixability of a logic circuit

Abstract

A device for testing the fixability of logic circuits having an embedded memory. The logic circuit includes a built-in test circuit for generating data which tests the embedded memory. An allocation logic circuit provides an output line for each bit of the memory identifying if the bit has either failed or passed. A Failed Data Bit Register is connected to the output lines. The Failed Data Bit Register includes a plurality of shift register stages. A multiplex circuit associated with each stage of the shift register receives as a first input the corresponding output line of the allocation logic circuit. A second input of the multiplex circuit connects to the preceding stage of the shift register. A clock cycle counter connects to an enabling line of the multiplex circuits and to a source of clock pulses. The clock cycle counter enables the plurality of multiplex circuits to cycle data from the allocation logic circuit through the plurality of stages until it is completely cycled through the plurality of stages. A fail counter is connected to the last stage and counts the number of times Failed Data Bits have been produced by recycling the data.