The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 06, 2001
Filed:
May. 01, 1997
Jeffrey Clay Dunnihoo, Austin, TX (US);
Standard Microsystems Corp., Hauppauge, NY (US);
Abstract
The present invention relates to a peripheral microcontroller for providing a high performance USB (Universal Serial Bus) connection to existing peripheral architectures (such as printers and disk drives with existing microcontrollers) and to new peripheral architectures (such as a 4-port USB-to-Ethernet Bridge). The USB peripheral microcontroller includes three units. A Serial Interface Engine (SIE) connects to a USB host or USB hub. A Microcontroller (MCU) Interface Unit connects to one or more peripheral devices such as ISA-like peripherals. A Memory Management Unit (MMU) provides a buffering mechanism between the SIE and MCU Interface Unit. The MMU utilizes a unique data packet buffering architecture. Packets received at the MMU from a peripheral for transmission to the USB host and packets received at the MMU from the USB host for transmission to a peripheral are buffered in a RAM. The capacity of the RAM is dynamically allocatable among various USB endpoints and the USB host so that the size of the RAM is minimized. The data path of the inventive USB peripheral controller is also highly advantageous. The SIE accesses the packet buffer RAM via a DMA controller in the MMU. The MCU Interface Unit accesses the packet buffer RAM via a microcontroller or a DMA controller. An arbiter in the MMU enables these multiple masters to access the packet buffer RAM.