The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 06, 2001
Filed:
May. 26, 2000
Shuichiro Kouchi, Tenri, JP;
Sharp Kabushiki Kaisha, Osaka, JP;
Abstract
A virtual-grounding memory cell array region and a virtual-grounding dummy cell array region are electrically isolated from each other while any increase in chip size is suppressed. An erase voltage Vers (−8 V) is applied to a dummy main bit line DMBL,in a dummy cell array region,via an erase voltage supply transistor,. A negative voltage (−8 V) is applied to drains of dummy cells DCELL,, DCELL,, . . . as well as sources of dummy cells DCELL,, DCELL,, . . . within a BLOCKn through dummy sub-bit lines DSBL. By electrons being injected into the floating gates of all the dummy cells DCELL in the columns of the dummy cells DCELL,and DCELL,within the BLOCKn, the threshold of those dummy cells DCELL becomes high. Occurrence of any charging currents and leak currents from the virtual-grounding memory cell array region to the floating capacitance of the dummy cells is prevented.