The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 06, 2001
Filed:
Apr. 08, 1999
Hyun D. Park, Greer, SC (US);
Joseph D. Nance, Central, SC (US);
Mike S. H. Chu, Lewiston, NY (US);
Yuval Avniel, Longmont, CO (US);
Other;
Abstract
Multilayer ceramic chip capacitors which satisfy X7R requirements and which are compatible with reducing atmosphere sintering conditions so that non-noble metals such as nickel, copper, and alloys thereof may be used for internal and external electrodes are made in accordance with the invention. The capacitors exhibit desirable dielectric properties (high capacitance, low dissipation factor, high insulation resistance), excellent performance on highly accelerated life testing, and very good resistance to dielectric breakdown. The dielectric layers preferably contain BaTiO,as the major component and CaTiO,, BaO, CaO, SrO, Si0,, MnO,, Y,O,, and CoO as minor components in such proportions so that there are present 0.1 to 4 mol % CaTiO,, 0.1 to 2 mol % BaO, 0 to 1 mol % CaO, 0 to 1 mol % SrO, 0.1 to 5 mol % SiO,, 0.01 to 2 mol % MnO2, 0.1 to 3 mol % Y,O,, and 0.01 to 1 mol % CoO. The preferred form of the invention may be sintered in the temperature range 1,250 to 1,400° C. in a reducing atmosphere having a humidified mixture of nitrogen and hydrogen. Additionally, a re-oxidation procedure may be utilized during the sintering cycle to optimize the resistance of the ceramic to dielectric breakdown.