The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 06, 2001

Filed:

Oct. 28, 1999
Applicant:
Inventors:

James D. MacDonald, Jr., Apex, NC (US);

Rahul Gupta, Apex, NC (US);

Assignee:

Ericsson Inc., Research Triangle Park, NC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/906 ;
U.S. Cl.
CPC ...
H01L 2/906 ;
Abstract

An integrated circuit includes an integrated circuit die having first and second opposing faces, a plurality of spaced apart bonding regions on the first face, and at least one groove in the second face. The at least one groove allows the die to flex upon application of stress to the bonding regions due to thermal cycling of the integrated circuit die, compared to absence of the at least one groove. Preferably, multiple grooves are provided, a respective one of which extends between a respective pair of adjacent spaced apart bonding regions. The grooves may be fabricated by sawing and/or etching the grooves in the second face. The sawing and/or etching may be performed at the wafer stage, before the integrated circuit dies are singulated. Alternatively, the sawing and/or etching may take place after the integrated circuit dies are singulated from the wafer.


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