The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 30, 2001
Filed:
Aug. 06, 1997
Richard A. Laubhan, Fort Collins, CO (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A method designates nets of a circuit for detailed parasitic impedance extraction (e.g., calculation of parasitic resistance and/or capacitance components of circuit interconnects) by comparing an estimated net impedance parameter with other circuit characteristics, such as the output resistance of a driver cell or the gate capacitance provided by load elements connected to the net. One or more threshold percentage parameters may be used in the comparison. Also, based on the designation, the estimated net impedance parameter or the detailed parasitic impedance value may be used for calculating logic delay through a logic cell driving the net. A program stored on a computer readable medium also operates to evaluate the parasitic impedance of circuit interconnects relative to other circuit characteristics and, depending on this evaluation, calculates the logic delay of a logic cell driving the net using an estimated net impedance parameter or detailed parasitic impedance parameter.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile