Circuit and method employing feedback for driving a clocking signal to compensate for load-induced skew

Abstract

A clock generation circuit is provided within an electronic computer system to adjust the phase of a clocking signal provided to various subsystems of the electronic system. A first phase-locked loop (PLL) is provided to establish multiple phases of a first reference clock. One of those phases is selected as a second reference clock, and a second PLL synchronizes the clocking signal to that second reference clock. Each subsystem and associated load which receives the clocking signal has a corresponding clock generation circuit comprising the second PLL. The second PLL for one subsystem can adjust the clocking signal phase prior to that subsystem receiving the clocking signal. The amount by which the second PLL adjusts phase on clocking signal may be different than that by which another, second PLL adjusts the clocking signal arriving on another subsystem. In all instances, however, the clocking signal arriving at the various subsystems are independently and variably changed to match the unique load characteristics of each subsystem using feedback of the clocking signal to the input of each respective second PLL.