The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 30, 2001
Filed:
Jul. 19, 1999
Matthew Glenn Waight, Pipersville, PA (US);
General Instrument Corporation, Horsham, PA (US);
Abstract
An oscillator is formed using a Field-Effect Transistor (FET) in a Colpitts configuration. The circuit has a resistor from source to ground. Also connected to the source are two capacitors, one between the source and ground while the other is from source to gate. These capacitors provide a phase-shifted feedback signal to the gate. Also connected to the gate is the varactor tank, which has a voltage variable reactance that is used to tune the oscillation to the desired frequency. Between the drain of the FET and the supply voltage is a resistor-capacitor network. Between two series resistors a shunt capacitor is added to minimize local oscillator leakage onto the Vdd line. The resistor network also provides impedance for the Pre-Scalar output, which is simply a connection to the drain of the FET. The pre-scalar output is used to provide a reference signal to the phase-locked loop, which generates the correction voltage to the oscillator's VCO input. It is at the pre-scalar output that a filter network is added to reduce the base-band noise from the Vdd line. By adding a shunt network, consisting of a small inductor and a low ESR capacitor, the supply noise is filtered without reducing the voltage or current supplied to the oscillator. The inductor removes the shunt capacitance at the oscillation frequency, avoiding any reduction in signal to the phase-locked loop circuit. The low ESR capacitor works with the resistance on-chip between the Vdd line and the drain to reduce the low frequency noise present at the FET's drain. This reduction in low-frequency noise results in improved phase noise performance without degrading any other circuit parameters.