The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2001

Filed:

Jul. 14, 1999
Applicant:
Inventor:

Shad R. Shepston, Firestone, CO (US);

Assignee:

Agilent Technologies, Palo Alto, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/00 ;
U.S. Cl.
CPC ...
H03K 3/00 ;
Abstract

Two complementary clocks that are well matched are produced from a single input clock. A clock buffer includes an alternating series of edge-rate-controlled inverters and level restoring inverters. The output of this series of inverters is compared to the input clock by a race timer. If the output of the series of inverters switches in the opposite direction before the input clock, the edge rates of the series of inverters are slowed down. If the output of the series of inverters switches in the opposite direction after the input clock, the edge rates of the series of inverters are speeded up. The output of the series of inverters eventually approaches the timing of the input clock but complemented. These signals form a pair of complementary clocks with well matched timing.


Find Patent Forward Citations

Shepston, Shad. (2001). Low mismatch complementary clock generator (U.S. Patent No. 6181185). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6181185

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…