The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 30, 2001
Filed:
Jun. 28, 1999
Krishna Rangasayee, Mountain View, CA (US);
Brad Ishihara, Sunnyvale, CA (US);
Kunio Nishiwaki, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A method of programming and verifying a macroscale based architecture in a field programmable logic device includes the step of selecting a flip-flop. The flip-flop contains a programmable address that accepts a sequence of instructions. A Switch Controller then selectably enables either one of two banks of switches. If the first bank of switches is selected, the programming operation is selected. If the second bank of switches is enabled, the verification operation is selected. The verification operation includes the step of automatically incrementing a base address through a set of incremented addresses. For each incremented address produced by the incrementing step, a margin low operation is performed with a Level Tester Array and a margin high operation is performed with a Level Tester Array. Thus, unlike the prior art, margin operations with the present invention are performed without using a macrocell scan register. Advantageously, relatively large groups of data are loaded into the flip-flops in the ADSR to improve processing.