The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2001

Filed:

Mar. 30, 1998
Applicant:
Inventor:

Harold S. Crafts, Colorado Springs, CO (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/144 ; H01L 2/131 ; H01L 2/1469 ; H01L 2/711 ;
U.S. Cl.
CPC ...
H01L 2/144 ; H01L 2/131 ; H01L 2/1469 ; H01L 2/711 ;
Abstract

A dynamic random access memory (DRAM) segment incorporates at least one shielding conductor spaced from a matrix of memory cells above the substrate and a well formed in the substrate which contains the memory cells. The shielding conductor primarily shields the memory cells from external noise signals created by other conductors. The isolating well primarily shields the memory cells from noise signals created by substrate currents and alpha particles. Among other features the DRAM employs a logically complementary pair of charge storage capacitors and differential sensing to avoid the influence of noise on a single memory capacitor. The shielding conductor is formed by a mesh of conductors or an integral conductor which overlays the matrix of cells and connects to the well. External power supplies and references are also connected to the well and the shielding conductors.


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