The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2001

Filed:

Jun. 09, 1998
Applicant:
Inventors:

Mitsuhiko Ogihara, Tokyo, JP;

Yukio Nakamura, Tokyo, JP;

Masumi Taninaka, Tokyo, JP;

Takatoku Shimizu, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 3/300 ;
U.S. Cl.
CPC ...
H01L 3/300 ;
Abstract

A high-density semiconductor device and semiconductor device array exhibiting high light emission efficiency which can be mass-produced at low cost with high yield is provided. An LED array comprises a structure wherein an n-type GaAs buffer layer,is formed on an n-type GaAs substrate,on which are then stacked an n-type Al,Ga,As layer,, an n-type Al,Ga,As layer,, a semi-insulating Al,Ga,As layer,, and a semi-insulating GaAs layer,. The energy band gaps of the Al,Ga,As layer,and Al,Ga,As layer,are at least larger than the energy band gap of the Al,Ga,As layer,. A pn junction is formed by selective diffusion, having a diffusion front in the semiconductor layer having the smaller energy band gap sandwiched between the semiconductor layers having the larger energy band gaps. The outermost layer forming ohmic contact is made a p-type GaAs region formed by zinc diffusion in a semi-insulating GaAs layer.


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