Method of manufacturing non-volatile memory device

Abstract

A method of manufacturing a non-volatile memory device is provided. According to an aspect of this method, an isolation layer is formed on a semiconductor substrate including a cell array part and a peripheral circuit part. A floating gate pattern is formed exposing the semiconductor substrate in the peripheral circuit part with a tunnel oxide layer interposed between the floating gate pattern and the semiconductor substrate in the cell array part, and an interlayer insulating layer covering the floating gate pattern is formed. A control gate layer is formed, which covers the interlayer insulating layer and the semiconductor substrate in the peripheral circuit part while interposing a gate oxide layer between the control gate layer and the semiconductor substrate. The isolation layer in the peripheral circuit part is protected by leaving a part of the control gate layer covering the peripheral circuit part, and a control gate, an interlayer insulating layer pattern, and a floating gate in the cell array part are formed by sequentially patterning the control gate layer, the interlayer insulating layer, and the floating gate pattern in the cell array part. A first low-concentration impurity layer is formed by first ion-implantation of arsenic into the semiconductor substrate adjacent to the floating gate using the control gate and the control gate layer covering the peripheral circuit part as an ion-implantation mask. A gate is formed in the peripheral circuit part by patterning the control gate layer in the peripheral circuit part with a photo resist pattern shielding the cell array part. A second low-concentration impurity layer is formed by second ion-implantation of second impurities, phosphorous, into the semiconductor substrate adjacent to the gate using the photo resist pattern as an ion-implantation mask.